TURlNG A WARD MllCROlPlPELlNES

The ,pipeline processor is a common paradigm for very high speed computing machinery. Pipeline processors provide high speed because their separate stages can operate concurrently, much as different people on a manufacturing assembly line work concurrently on material passing d0w.n the line. Although the concurrency of pipeline processors makes their design a demanding task, they can be Found in graphics processors, in signal processing devices, in integrated circuit components for doing arithmetic, and in the instruction interpretation units and arithmetic operations of general purpose computing machinery. Because I plan :o describe a variety of pipeline processors, I will start by suggesting names for their various forms. Pipeline processors, or more simply just pipelines, operate on data as it passes along them. The latency of a pipeline is a measure of how long it takes a single data value to pass through it. The throughput rate of a pipeline is a measure of how many data values can pass through it per unit time. Pipelines both store and process data; the storage elements and proce:#sing logic in them alternate along their length. I wi .l describe pipelines in their complete form later, but first I will focus on their storage elements alone, stripping away all processing logic. Stripped of all processing logic, any pipeline acts like a series of storage elements through which data can pass. Pipelines can tie clocked or event-driven, depending on whether their parts act in response to some widelydistributed external clock, or act independently whenever local events permit. Some pipelines are inelastic; the amount of ds ta in them is fixed. The input rate and the output rate of an inelastic pipeline must match exactly. Stripped 0:’ any processing logic, an inelastic pipeline acts like a shift register. Other pipelines are elastic; the amount of d:.ta in them may vary. The input rate and the output rate of an elastic pipeline may differ momentarily because of internal buffering. Stripped of all processing logic, an elastic pipeline becomes a flowthrough first-in-:irst-out memory, or FIFO. FIFOs may be clocked or event-driven; their important property is